1. Field of the Invention
The present invention relates to encoding devices, and more particularly to encoding devices allowing multiplexing of a video signal and an audio signal according to a predetermined compression encoding standard.
2. Description of the Background Art
Recently, MPEG2 (Moving Picture Experts Group) has become widely adopted as an international standard of data compression encoding in various applications including digital satellite broadcasting and DVD (Digital Versatile Disc). MPEG2 standard, defined in three layers, that is, video, audio and system layers, allows multiplexing of a video signal and an audio signal.
In general, according to MPEG2 standard, audio data compression and a process relating to a system do not require an excessively enormous and complicated operation, whereas an operation for video data compression is complicated and the amount of operation is enormous.
In a multiplexing of an audio signal and a video signal according to the conventional MPEG2 standard, generally the process relating to the audio and the system is realized through a software process in a processor unit, whereas the process relating to video is realized through a dedicated hardware, which is controlled through a software process in the processor unit.
Encoding devices performing such multiplexing are, therefore, implemented as multiplexing encoding systems formed as a combination of three devices, that is, an audio compression encoding device and a system multiplexing device both realized with a DSP (Digital Signal Processor), for example, in a software-like manner, and a video compression encoding device including an LSI (Large Scale Integrated Circuit) dedicated for image compression and a processor unit controlling the LSI.
With reference to FIG. 12, a multiplexing encoding system 300 of the conventional art includes a video compression encoding device 400 performing a video encoding process on a video signal, an audio compression encoding device 500 performing an audio encoding process on an audio signal and a system multiplexing device 600 performing a system process for multiplexing encoded video data and encoded audio data.
Video compression encoding device 400 performs a compression encoding of original video data supplied to a video input terminal 402 to generate encoded video data. Audio compression encoding device 500 performs a compression encoding of original audio data supplied to an audio input terminal 502 to generate encoded audio data.
System multiplexing device 600 receives encoded video data and encoded audio data from video compression encoding device 400 and audio compression encoding device 500, respectively, performs a multiplexing process according to a format defined by a system layer of MPEG2 standard, for example, generates and outputs resulting compressed data via an output terminal 606. The compression encoding process will also be referred to as an encoding process hereinbelow.
With reference to FIG. 13, video compression encoding device 400 includes a video encoding unit 420 encoding original video data supplied to video input terminal 402, a processor unit 410 controlling the encoding process at video encoding unit 420, an FIFO (First In First Out) buffer 455 receiving encoded video data generated in video encoding unit 420, a video timing generation unit 430 generating a timing signal for controlling a timing of execution of the video encoding process and an internal bus 450. The encoded video data supplied to FIFO buffer 455 is output via a video output terminal 406. Processor unit 410 is connected to video encoding unit 420 via internal bus 450. As video encoding unit 420, an image compression LSI, which is a dedicated hardware, is employed, for example.
Video encoding unit 420 includes a register 422 to hold a control parameter employed in the video encoding process. The control parameter held by register 422 is set through processor unit 410 via internal bus 450. The timing signals generated from video timing generation unit 430 include a picture timing signal PSYNC indicating an activation timing of a picture-related process and a macro block timing signal MBSYNC indicating an activation timing of a macro block-related process (hereinafter referred to also as MB process) in MPEG2 standard, for example.
FIG. 14 shows a timing chart referenced for describing an execution timing of the video encoding process.
With reference to FIG. 14, the picture-related process is executed in response to the generation of picture timing signal PSYNC and the MB process is executed in response to the generation of macro block timing signal MBSYNC.
In the video compression encoding, the number of frames n (n is a natural number) included in a second is determined and a cycle of the generation of picture timing signal PSYNC is 1/n second. For example, when thirty frames are included in a second, the cycle of picture timing signal PSYNC is 1/30 second.
In MPEG2 standard, the video compression encoding is executed with a one-frame image divided into macro blocks (hereinafter referred to simply as MB) serving as a unit of processing, of sixteen pixelsxc3x97sixteen lines. If an image of one frame is formed from 720 pixels in a vertical directionxc3x97480 lines in a horizontal direction, one frame includes 1350 MB""s. Then, video timing generation unit 430 generates 1350 macro block timing signals MBSYNC during one cycle of picture timing signal PSYNC.
Video encoding section 420 operates in response to timing signals PSYNC and MBSYNC. In particular, video encoding unit 420 executes the MB process for each MB in response to macro block timing signal MBSYNC and executes the picture-related process which is common to all MB included in one frame in response to picture timing signal PSYNC.
A necessary control parameter for the picture-related process and the macro block-related process is set in register 422 through processor unit 410. Processor unit 410, hence, must operate in synchronization with timing signals PSYNC and MBSYNC.
When these timing signals PSYNC and MBSYNC generated from video timing generation unit 430 are supplied to an interrupt terminal of processor unit 410, processor unit 410 can execute an operation corresponding to the picture-related process and the macro block-related process as an interrupt process in synchronization with video encoding unit 420.
With reference to FIG. 15, audio compression encoding device 500 includes an FIFO buffer 532 receiving original audio data supplied to audio input terminal 502, a processor unit 510 including a software for executing an encoding process on the original audio data, an FIFO buffer 534 receiving encoded audio data supplied from processor unit 510, an audio output terminal 505 supplying the encoded audio data supplied from FIFO buffer 534, and an internal bus 550. Processor unit 510 is connected to FIFO buffers 532 and 534 via internal bus 550.
The original audio data supplied to audio input terminal 502 is then supplied to FIFO buffer 532. Processor unit 510 reads the original audio data from FIFO buffer 532 via internal bus 550. Processor unit 510 encodes the read original audio data according to an internally stored program to generate encoded audio data. The encoded audio data is written into FIFO buffer 534 via internal bus 550.
The encoded audio data supplied to FIFO buffer 534 is output from audio output terminal 505. The activation of the program for executing the audio encoding process in processor unit 510 is controlled through an audio timing generation unit 520.
With reference to FIG. 16, the audio encoding process in processor unit 510 is activated in response to generation of a timing signal FSYNC. When a sampling frequency of 48 kHz according to a layer II of the MPEG1 audio standard is employed as a mode for the audio encoding process, a frame defined by 1152 samples will be processed as one unit.
A length of one frame, then, becomes 1152 samples/48 kHz=0.024 sec and the processing of one frame must be completed every 24 msec to allow a smooth audio encoding. For the smooth operation, audio timing generation unit 520 generates timing signal FSYNC at a cycle of 24 msec and supplies the signal to the interrupt terminal of processor unit 510.
In response to an interrupt request through audio timing signal FSYNC, processor unit 510 activates a software for performing the audio compression encoding and executes the audio encoding process for each frame.
With reference to FIG. 17, system multiplexing device 600 includes an encoded video data input terminal 602 receiving an input of encoded video data, an FIFO buffer 652 provided corresponding to the encoded video data, an encoded audio data input terminal 604 receiving encoded audio data, an FIFO buffer 654 provided corresponding to the encoded audio data, a processor unit 610 controlling the multiplexing process, a header memory 640 holding header data of multiplexed compressed data stream and an internal bus 650.
System multiplexing device 600 further includes a multiplexing control unit 620 receiving header data output from header memory 640, encoded video data supplied from FIFO buffer 652 and encoded audio data from FIFO buffer 654, and selectively transferring one type of data to FIFO buffer 656, a compressed data output terminal 606 supplying the compressed data stream supplied from FIFO buffer 656, and a status generation unit 630 generating a timing signal BSOREQ for requesting a supply of new compressed data according to data amount in FIFO buffer 656.
Processor unit 610 generates and supplies header data to header memory 640 via internal bus 650. In addition, processor unit 610 sets via internal bus 650 a control parameter in a register 625, which parameter is provided in multiplexing control unit 620, for designating a selective transfer of data in multiplexing control unit 620.
When a format of a transport stream (hereinafter also referred to simply as TS) is adopted according to the MPEG2 system layer standard, for example, data is sequentially transferred to an FIFO buffer 656 in the order of 4-byte header data, 184-byte compressed (encoded) video data, 4-byte header data, and 184-byte compressed (encoded) audio data, thus encoded video data and encoded audio data are multiplexed and compressed data thereof can be generated.
In this case, which type of encoded data is to be transferred by how much data amount in what order, and so on, can be controlled through the setting of control parameters held in register 625 through processor unit 610.
In a system generally supplying TS data as compressed data, in most cases compressed data output terminal 606 is connected to a transmission line. In this case, compressed data must be output at a constant rate. The amount of data held in FIFO buffer 656 is, therefore, monitored through status generation unit 630, which generates and supplies timing signal BSOREQ to the interrupt terminal of processor unit 610 when the empty area of FIFO buffer 656 becomes larger than 188 bytes which corresponds to a constituent unit of the TS data, for example. In response, processor unit 610 indicates to multiplexing control unit 620 to transfer new multiplexed compressed data to FIFO buffer 656.
An encoding system allowing the multiplexing of the audio signal and the video signal can be thus provided, with the video compression device employing the image compression LSI which is a dedicated hardware device, the audio compression encoding device and the system multiplexing device both executing a software process corresponding to a program stored in the processor unit.
Because of the advancement in LSI integration in recent years, however, the integration of the video compression encoding device, the audio encoding device and the system multiplexing device on one LSI chip has become possible.
On the other hand, the video encoding process, the audio encoding process and the system process must be executed independent from each other at a predetermined cycle as described above. Hence, if these devices are arranged on the same LSI in the encoding device and share the same resources for plurality of processes, the control of the order of process execution becomes important when activation requests for the plurality of processes are made such that their execution overlap.
An object of the present invention is to provide an encoding device mountable on one LSI chip, for multiplexing a video signal and an audio signal while effectively sharing resources for different processes.
In brief, the present invention is an encoding device multiplexing an input video signal and an input audio signal according to a predetermined compression encoding standard, which encoding device includes: a processor unit, a timing control unit, a first buffer, a video encoding process unit, a second buffer, a third buffer and a multiplex process unit.
The processor unit has a function of executing an audio encoding process to convert the audio signal to encoded audio data, a function of executing a first control process for controlling a video encoding process and a function of executing a second control process for controlling a system process. The timing control unit generates at least one first timing signal for activating the video encoding process, a second timing signal for activating the audio encoding process and a third timing signal for activating the system process. The first buffer holds the encoded audio data temporarily. The video encoding process unit is activated in response to the first timing signal and executes the video encoding process to convert the video signal to encoded video data. The second buffer holds the encoded video data temporarily. The third buffer holds header data generated from the processor unit. The multiplex process unit executes the system process according to an indication from the processor unit and sequentially outputs the encoded video data, the encoded audio data and the header data supplied from first, second and third buffers, respectively, by an amount and in an order according to a system process parameter. The processor unit includes an interrupt control circuit receiving at least one of first, second and third timing signals to designate for an interrupt process one of the audio compression process, first and second control processes in response to generation of each timing signal supplied as an input. The processor unit preferentially executes the interrupt process.
Thus, a main advantage of the present invention lies in that mounting of the encoding device on a single LSI chip is allowed as the processor unit is shared for the video encoding process, the audio encoding process and the system process.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.